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integrated circuit systems, inc. ics932s203 0601e?12/22/04 block diagram recommended application: servers based on intel ck408 processors output features: 4 differential cpu clock pairs @ 3.3v 7 pci (3.3v) @ 33.3mhz 3 pci_f (3.3v) @ 33.3mhz 1 usb (3.3v) @ 48mhz 1 dot (3.3v) @ 48mhz 1 ref (3.3v) @ 14.318mhz 1 3v66 (3.3v) @ 66.6mhz 1 vch/3v66 (3.3v) @ 48mhz or 66.6mhz 3 66mhz_out/3v66 (3.3v) @ 66.6mhz_in or 66.6mhz 1 66mhz_in/3v66 (3.3v) @ input/66mhz features: supports spread spectrum modulation, down spread 0 to -0.5%. efficient power management scheme through pd# and pci_stop#. uses external 14.318mhz crystal stop clocks and functional control available through smbus interface. key specifications: ? cpu output jitter <150ps 3v66 output jitter <250ps cpu output skew <150ps pin configuration 56-pin 300mil ssop/tssop frequency generator with 133mhz differential cpu clocks functionality * these inputs have 150k internal pull-up resistor to vdd. 1 s f0 s f u p c ) z h m ( 6 6 v 3 ) z h m ( ] 0 : 2 [ f f u b 6 6 ] 2 : 4 [ 6 6 v 3 ) z h m ( f _ i c p i c p ) z h m ( 10 0 0 16 . 6 6h t a p n i 6 . 6 62 / n i 6 . 6 6 11 3 . 3 3 16 . 6 6h t a p n i . 6 62 / n i 6 . 6 6 00 0 0 16 . 6 66 . 6 63 . 3 3 01 3 . 3 3 16 . 6 66 . 6 63 . 3 3 d i m0 z - i hz - i hz - i hz - i h d i m1 2 / k l c t4 / k l c t4 / k l c t8 / k l c t
2 ics932s203 0601e?12/22/04 pin configuration r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d , 6 2 , 9 1 , 4 1 , 8 , 1 0 5 , 6 4 , 7 3 , 2 3 d d vr w py l p p u s r e w o p v 3 . 3 21 xt u p n i l a t s y r c 2 xt u p n i l a t s y r c z h m 8 1 3 . 4 1 32 x l a t s y r c 1 x t u p t u o t u p t u o l a t s y r c z h m 8 1 3 . 4 1 5 , 6 , 7) 0 : 2 ( f _ k l c i c pt u o . t n e m e g a n a m r e w o p r o f # p o t s _ i c p y b d e t c e f f a t o n k c o l c i c p g n i n n u r e e r f , 7 2 , 0 2 , 5 1 , 9 , 4 7 4 , 1 4 , 6 3 , 1 3 d n gr w py l p p u s v 3 . 3 r o f s n i p d n u o r g , 3 1 , 6 1 , 7 1 , 8 1 0 1 , 1 1 , 2 1 ) 0 : 6 ( k l c i c pt u os t u p t u o k c o l c i c p 1 2 , 2 2 , 3 2 ) 0 : 2 ( t u o _ z h m 6 6t u o. t u p n i n i _ z h m 6 6 m o r f t u o _ z h m 6 6 d e r e f f u b z h m 6 6 ) 2 : 4 ( 6 6 v 3t u oo c v l a n r e t n i m o r f , s k c o l c e c n e r e f e r z h m 6 6 4 2 n i _ z h m 6 6n is k c o l c i c p d n a t u o _ z h m 6 6 d e r e f f u b o t t u p n i z h m 6 6 5 _ 6 6 v 3t u oo c v l a n r e t n i m o r f , k c o l c e c n e r e f e r z h m 6 6 5 2# d pn i. w o l e v i t c a . e d o m n w o d - r e w o p s e k o v n i 8 2# d g r w p _ t t v n i e n i m r e t e d o t d e s u e b o r t s e v i t i s n e s l e v e l a s i t u p n i l t t v l v 3 . 3 s i h t e b o t y d a e r e r a d n a d i l a v e r a s t u p n i 0 l e s i t l u m d n a ] 2 : 0 [ s f n e h w d e l p m a s ) w o l e v i t c a ( 9 2a t a d s o / i t n a r e l o t v 5 y r t i u c r i c s u b m s r o f n i p a t a d 0 3k l c s n i t n a r e l o t v 5 y r t i u c r i c s u b m s f o n i p k c o l c 3 30 _ 6 6 v 3t u oo c v l a n r e t n i m o r f , s k c o l c e c n e r e f e r z h m 6 6 4 3# p o t s _ i c pn i t p e c x e w o l t u p n i n e h w , l e v e l 0 c i g o l t a s k c o l c k l c i c p s t l a h g n i n n u r e e r f e r a h c i h w f _ k l c i c p 5 3k l c _ h c v / 1 _ 6 6 v 3t u o h g u o r h t e l b a t c e l e s t u p t u o v 3 . 3 i 2 c r o o c v l a n r e t n i m o r f z h m 6 6 e b o t ) c s s - n o n ( z h m 8 4 8 3t o d _ z h m 8 4t u ot o d r o f k c o l c t u p t u o z h m 8 4 9 3b s u _ z h m 8 4t u ob s u r o f k c o l c t u p t u o z h m 8 4 5 5 , 0 4) 0 : 1 ( s fn in o i t c e l e s e d o m r o f t u p n i v 3 . 3 l a i c e p s 2 4f e r it u o n i p s i h t . s r i a p k l c u p c e h t r o f t n e r r u c e c n e r e f e r e h t s e h s i l b a t s e n i p s i h t e h t h s i l b a t s e o t r e d r o n i d n u o r g o t d e i t r o t s i s e r n o i s i c e r p d e x i f a s e r i u q e r . t n e r r u c e t a i r p o r p p a 3 40 l e s t l u mn i o t r o i r p d e h c t a l y l l a n r e t n i n e h t d n a p u - r e w o p n o d e s n e s s i t u p n i 0 l e s t l u m . s k c o l c z h m 8 1 3 . 4 1 v 3 n o t u p t u o r o f d e s u g n i e b n i p e h t 3 5 , 1 5 , 8 4 , 4 4) 0 : 3 ( c k l c u p ct u o t n e r r u c e r a e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " y r a t n e m e l p m o c " . s a i b e g a t l o v r o f d e r i u q e r e r a s r o t s i s e r l a n r e t x e d n a s t u p t u o 4 5 , 2 5 , 9 4 , 5 4) 0 : 3 ( t k l c u p ct u o d n a s t u p t u o t n e r r u c e r a e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " e u r t " . s a i b e g a t l o v r o f d e r i u q e r e r a s r o t s i s e r l a n r e t x e 6 5f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 power groups (analog) vdda = pll1 vdd48 = 48mhz, pll vddref = vdd for xtal, por (digital) vddpci vdd3v66 vddcpu
3 ics932s203 0601e?12/22/04 frequency select table host swing select functions 0 l e s i t l u m t e g r a t d r a o b z m r e t / e c a r t , r e c n e r e f e r = f e r i v d d ) r r * 3 ( / t u p t u o t n e r r u c z @ h o v 0s m h o 0 5 , % 1 1 2 2 = r r a m 0 0 . 5 = f e r i f e r i * 4 = h o i0 5 @ v 0 . 1 1s m h o 0 5 , % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 6 = h o i0 5 @ v 7 . 0 fs2 fs1 cpu 3v66 (1:0) 66buff (2:0) / 3v66 ( 4:2 ) 66 in / 3v66_5 pci ref usb, dot note 1 0 100 66.6 66.6 in path 66.6 in 66.6 in/2 14.318 48 buffer mode 66 1 1 133.3 66.6 66.6 in path 66.6 in 66.6 in/2 14.318 48 buffer mode 66 0 0 100 66.6 66.6 66.6 33.3 14.318 48 driven 66 0 1 133.3 66.6 66.6 66.6 33.3 14.318 48 driven 66 mid 0 hi-z hi-z hi-z hi-z hi-z hi-z hi-z tri-state outputs mid 1 tclk/2 tclk/4 tclk/4 tclk/4 tclk/8 tclk tclk/2 tclk is at x1 input
4 ics932s203 0601e?12/22/04 byte 0: control register notes: 1. r= read only rw= read and write 2. pwd = power on default 3. the purpose of this bit is to allow a system designer to implement pci_stop functionality in one of two ways. wither the system designer can choose to use the externally provided pci_stop# pin to assert and de-assert pci_stop functionality via smbus byte 0 bit 3. in hardware mode it is not allowed to write to the smbus byte 0 bit3. in software mode it is not allowed to pull the external pci_stop pin low. this avoids the issues related with hardware started and software stopped pci_stop conditions. the clock chip is to be operated in the hardware or software pci_stop mode only, it is not allowed to mix these modes. in hardware mode the smbus byte 0 bit 3 is r/w and should reflect the status of the part. whether or not the chip is in pci_stop mode. functionality pci_stop mode should be entered when [(pci_stop#=0) or (smbus byte 0 bit 3 = 0)]. byte 1: control register t i b# n i pe m a nd w pe p y tn o i t p i r c s e d 0 t i b- 1 ) d e v r e s e r ( 1 t i b5 50 s fxr p u r e w o p n o d e l p m a s n i p 0 s f f o e u l a v e h t s t c e l f e r 2 t i b0 41 s fxr p u r e w o p n o d e l p m a s n i p 1 s f f o e u l a v e h t s t c e l f e r 3 t i b4 3# p o t s _ i c p 3 xr # p o t s _ i c p f o e u l a v e h t s t c e l f e r : e d o m e r a w d r a h d w p n o d e l p m a s n i p 4 t i b- 1 ) d e v r e s e r ( 5 t i b5 3h c v / 1 _ 6 6 v 30w r z h m 8 4 / z h m 6 6 t c e l e s h c v z h m 8 4 = 1 , z h m 6 6 = 0 6 t i b- 0 ) d e v r e s e r ( 7 t i b- d a e r p s d e l b a n e 0w rn o d a e r p s = 1 , f f o d a e r p s = 0 t i b# n i pe m a nd w pe p y tn o i t p i r c s e d 0 t i b1 5 , 2 5 0 t k l c u p c 0 c k l c u p c 1w rd e l b a n e = 1 d e l b a s i d = 0 1 t i b8 4 , 9 4 1 t k l c u p c 1 c k l c u p c 1w rd e l b a n e = 1 d e l b a s i d = 0 2 t i b4 4 , 5 4 2 t k l c u p c 2 c k l c u p c 1w rd e l b a n e = 1 d e l b a s i d = 0 3 t i b1 5 , 2 50-d e v r e s e r 4 t i b8 4 , 9 40-d e v r e s e r 5 t i b4 4 , 5 40-d e v r e s e r 6 t i b4 5 , 3 5 3 t k l c u p c 3 c k l c u p c 1w rd e l b a n e = 1 d e l b a s i d = 0 7 t i b3 40 l e s t l u mxr 0 l e s t l u m f o e u l a v t n e r r u c e h t s t c e l f e r
5 ics932s203 0601e?12/22/04 byte 2: control register notes: 1. r= read only rw= read and write 2. pwd = power on default t i b# n i pe m a nd w pe p y tn o i t p i r c s e d 0 t i b0 10 k l c i c p1w rd e l b a n e = 1 d e l b a s i d = 0 1 t i b1 11 k l c i c p1w rd e l b a n e = 1 d e l b a s i d = 0 2 t i b2 12 k l c i c p1w rd e l b a n e = 1 d e l b a s i d = 0 3 t i b3 13 k l c i c p1w rd e l b a n e = 1 d e l b a s i d = 0 4 t i b6 14 k l c i c p1w rd e l b a n e = 1 d e l b a s i d = 0 5 t i b7 15 k l c i c p1w rd e l b a n e = 1 d e l b a s i d = 0 6 t i b8 16 k l c i c p1w rd e l b a n e = 1 d e l b a s i d = 0 7 t i b- - 0 - ) d e v r e s e r ( byte 3: control register byte 4: control register t i b# n i pe m a nd w pe p y tn o i t p i r c s e d 0 t i b1 22 - 6 6 v 3 / 0 t u o _ z h m 6 61w rd e l b a n e = 1 d e l b a s i d = 0 1 t i b2 23 - 6 6 v 3 / 0 t u o _ z h m 6 61w rd e l b a n e = 1 d e l b a s i d = 0 2 t i b3 24 - 6 6 v 3 / 0 t u o _ z h m 6 61w rd e l b a n e = 1 d e l b a s i d = 0 3 t i b4 25 _ 6 6 v 31w rd e l b a n e = 1 d e l b a s i d = 0 4 t i b5 3k l c _ h c v / 1 _ 6 6 v 31w rd e l b a n e = 1 d e l b a s i d = 0 5 t i b3 30 _ 6 6 v 31w rd e l b a n e = 1 d e l b a s i d = 0 6 t i b- - 0 r ) d e v r e s e r ( 7 t i b- - 0 r ) d e v r e s e r ( t i b# n i pe m a nd w pe p y tn o i t p i r c s e d 0 t i b5 0 f _ k l c i c p1w rd e l b a n e = 1 d e l b a s i d = 0 1 t i b6 1 f _ k l c i c p1w rd e l b a n e = 1 d e l b a s i d = 0 2 t i b7 2 f _ k l c i c p1w rd e l b a n e = 1 d e l b a s i d = 0 3 t i b5 0 f _ k l c i c p0w r f o n o i t r e s s a h t i w 0 f _ k l c i c p f o l o r t n o c w o l l a g n i n n u r e e r f t o n = 1 , g n i n n u r e e r f = 0 . # p o t s _ i c p 4 t i b6 1 f _ k l c i c p0w r f o n o i t r e s s a h t i w 1 f _ k l c i c p f o l o r t n o c w o l l a g n i n n u r e e r f t o n = 1 , g n i n n u r e e r f = 0 . # p o t s _ i c p 5 t i b7 2 f _ k l c i c p0w r f o n o i t r e s s a h t i w 2 f _ k l c i c p f o l o r t n o c w o l l a g n i n n u r e e r f t o n = 1 , g n i n n u r e e r f = 0 . # p o t s _ i c p 6 t i b9 3b s u _ z h m 8 41w rd e l b a n e = 1 d e l b a s i d = 0 7 t i b8 3t o d _ z h m 8 41w rd e l b a n e = 1 d e l b a s i d = 0
6 ics932s203 0601e?12/22/04 byte 6: vendor id register (1 = enable, 0 = disable) t i b# n i pe m a nd w pe p y tn o i t p i r c s e d 0 t i bx 0 t i b d i r o d n e v1r) d e v r e s e r ( 1 t i bx 1 t i b d i r o d n e v0r) d e v r e s e r ( 2 t i bx 2 t i b d i r o d n e v0r) d e v r e s e r ( 3 t i bx 3 t i b d i r o d n e v0r) d e v r e s e r ( 4 t i bx 0 t i b d i n o i s i v e rxr n o d e s a b e b l l i w s e u l a v d i n o i s i v e r n o i s i v e r s ' e c i v e d l a u d i v i d n i 5 t i bx 1 t i b d i n o i s i v e rxr 6 t i bx 2 t i b d i n o i s i v e rxr 7 t i bx 3 t i b d i n o i s i v e rxr byte 5: programming edge rate (1 = enable, 0 = disable) notes: 1. r= read only rw= read and write 2. pwd = power on default t i b# n i pe m a nd w pe p y tn o i t p i r c s e d 0 t i bx b s u _ z h m 8 40w rl o r t n c e t a r e g d e b s u 1 t i bx b s u _ z h m 8 40w rl o r t n c e t a r e g d e b s u 2 t i bx t o d _ z h m 8 40w rl o r t n o c e t a r e g d e t o d 3 t i bx t o d _ z h m 8 40w rl o r t n o c e t a r e g d e t o d 4 t i bx - 0 - ) d e v r e s e r ( 5 t i bx - 0 - ) d e v r e s e r ( 6 t i bx - 0 - ) d e v r e s e r ( 7 t i bx - 0 - ) d e v r e s e r (
7 ics932s203 0601e?12/22/04 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter s ymbo l conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in = v dd -5 5 ma i il1 v in = 0 v; inputs with no pull-up resistors -5 ma i il2 v in = 0 v; inputs with pull-up resistors -200 operating supply current i dd3.3op c l = full load; select @ 100 mhz 229 230 360 ma i dd3.3op c l =full load; select @ 133 mhz 220 233 360 ma powerdown current i dd3.3pd 60 ma input frequency f i v dd = 3.3 v 14.318 mhz pin inductance l p in 7nh c in logic inputs 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target frequency 3 ms settlin g time 1 t s from 1st crossing to 1% target frequency 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target frequency 3 ms t pzh ,t pzl output enable delay (all outputs) 1 10 ns t phz ,t plz output disable delay (all outputs) 1 10 ns 1 guaranteed by design, not 100% tested in production. delay 1 input capacitance 1 input low current
8 ics932s203 0601e?12/22/04 electrical characteristics - cpu 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf parameter symbol conditions min typ max units notes current source output im p edance zo 1 v o = v x 3000 ? 1 voltage high vhigh 660 770 850 1 voltage low vlow -150 5 150 1 max volta g e vovs 756 1150 1 min volta g e vuds -300 -7 1 crossin g volta g e ( abs ) vcross ( abs ) 250 350 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all ed g es 12 140 mv 1 lon g accurac y pp m see t p eriod min-max values -300 300 pp m1,2 200mhz nominal 4.9985 5.0015 ns 2 200mhz s p read 4.9985 5.0266 ns 2 166.66mhz nominal 5.9982 6.0018 ns 2 166.66mhz s p read 5.9982 6.0320 ns 2 133.33mhz nominal 7.4978 7.5023 ns 2 133.33mhz s p read 7.4978 5.4000 ns 2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz s p read 9.9970 10.0533 ns 2 200mhz nominal 4.8735 ns 1,2 166.66mhz nominal/s p read 5.8732 ns 1,2 133.33mhz nominal/s p read 7.3728 ns 1,2 100.00mhz nominal/s p read 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 332 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 344 700 ps 1 rise time variation d-t r 30 125 ps 1 fall time variation d-t f 30 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 49 55 % 1 skew t sk3 v t = 50% 8 100 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 60 150 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref output is at 14.31818mhz tperiod average period absolute min period t absmin statistical measurement on single ended signal using oscilloscope math function. mv measurement on single ended signal using absolute value. mv
9 ics932s203 0601e?12/22/04 electrical characteristics - pciclk un-buffered mode t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 33 55 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.55 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -33 -33 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.32 0.5to 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.39 0.5 to 2 ns duty cycle d t1 1 v t = 1.5 v 45 52 55 % skew t sk1 1 v t = 1.5 v 247 500 ps jitter,cycle to cyc t jcyc-cyc 1 v t = 1.5 v 111 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - pciclk buffered mode t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 33 55 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.55 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -33 -33 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.29 0.5to 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.32 0.5 to 2 ns duty cycle d t1 1 v t = 1.5 v 45 51.9 55 % skew t sk1 1 v t = 1.5 v 209 500 ps jitter,cycle to cyc t jcyc-cyc 1 v t = 1.5 v 107 500 ps 1 guaranteed by design, not 100% tested in production.
10 ics932s203 0601e?12/22/04 electrical characteristics- 3v66 - buffer ed mode: 3v66 [1:0] 66mhz_out [2:0] t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 66.66 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 33 55 w output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.55 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -33 -33 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.44 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.36 2 ns duty cycle d t1 1 v t = 1.5 v 45 54.6 55 % skew t sk1 1 v t = 1.5 v 3v66 [1:0] 105 250 ps jitter t j c y c-c y c 1 v t = 1.5 v 3v66 [1:0] 121 300 ps skew t sk1 1 v t = 1.5 v 66mhz_out [2:0] 169 250 ps jitter t jcyc-cyc 1 v t = 1.5 v 66mhz_out [2:0] 89 300 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - 3v66 -un-buffered mode: 3v66 [5:0] t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 66.66 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 33 55 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.55 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -33 -33 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.38 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.45 2 ns duty cycle d t1 1 v t = 1.5 v 45 54.4 55 % skew t sk1 1 v t = 1.5 v 90 250 ps jitter t jcyc-cyc 1 v t = 1.5 v 3v66 128 250 ps 1 guaranteed by design, not 100% tested in production.
11 ics932s203 0601e?12/22/04 electrical characteristics - ref t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 mhz output impedance r dsp1 1 v o = v dd *(0.5) 20 48 60 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -29 -23 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1 1.25 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1 1.15 2 ns duty cycle d t1 1 v t = 1.5 v 45 53 55 % jitter t jcyc-cyc 1 v t = 1.5 v 723 1000 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - vch, 48mhz dot, 48mhz, usb t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 48 mhz output impedance r dsp1 1 v o = v dd *(0.5) 20 48 60 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -29 -23 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma 48dot rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 0.6 1 ns 48dot fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 0.8 1 ns vch 48 usb rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1 1.2 2 ns vch 48 usb fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1 1.3 2 ns 48 dot duty cycle d t1 1 v t = 1.5 v 45 52.8 55 % vch 48 usb duty cycle d t1 1 v t = 1.5 v 45 53.5 55 % 48 dot jitter t j c y c-c y c 1 v t = 1.5 v 183 350 ps vch jitter t jcyc-cyc 1 v t = 1.5 v 223 350 ps 1 guaranteed by design, not 100% tested in production.
12 ics932s203 0601e?12/22/04 1. the ics clock generator is a slave/receiver, smbus component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator smbus interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general smbus serial interface information the information in this section assumes familiarity with smbus programming. for more information, contact ics for an smbus software program. how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending first byte (byte 0) through byte 5 ics clock will acknowledge each byte one at a time . controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends first byte (byte 0) through byte 6 controller (host) will need to acknowledge each byte controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d2 (h) ac k dummy command code ac k dummy byte count ack byte 0 ac k byte 1 ac k byte 2 ack byte 3 ac k byte 4 ac k byte 5 ack byte 6 ack stop bit how to write: controller (host) ics (slave/receiver) start bit address d3 (h) ac k byte coun t ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack stop bit how to read:
13 ics932s203 0601e?12/22/04 all 3v66 clocks are to be in phase with each other. all 66mhz_out clocks are to be in phase with each other. there is no phase relationship between the 3v66 clocks and the 66mhz_out and pci clocks. in the case where 3v66_1 is configured as 48mhz vch clock, there is no defined phase relationship between 3v66_1/vch and other 3v66 clocks. the pci group should lag 3v66 by the standard skew described below as tpci. the 66mhz_in to 66mhz_out delay is shown in the figure below and is specified to be within a min and max propagation value. 66mhz_in 66mhz_out pciclk_f 3v66 tpd tpci no relationship buffered mode - 3v66[0:1], 66mhz_in, 66mhz_out[0:2] and pci phase relationship group skews at common transition edges: (buffered mode) group symbol conditions min typ max units 3v66 3v66 3v66 (1:0) pin to pin skew 0 500 ps 66mhz_out 66out 66mhz_out (2:0) pin to pin skew 0 175 ps pci pci pci_f (2:0) and pci (6:0) pin to pin skew 0 500 ps 66mhz_in 66mhz_out tpd propogation delay from 66mhz_in to 66mhz_out (2:0) 2.5 4.5 ns 66mhz_out to pci tpci 66mhz_out (2:0) leads 33 mhz pci 1.5 3.5 ns 1 guaranteed by design, not 100% tested in production.
14 ics932s203 0601e?12/22/04 all 3v66 clocks are to be in pphase with each other. in the case where 3v66_1 is configured as 48mhz vch clock, there is no defined phase relationship between 3v66_1/vch and other 3v66 clocks. the pci group should lag 3v66 by the standard skew described below as tpci. un-buffered mode 3v66 & pci phase relationship 3v66 (1:0) 3v66 (4:2) 3v66_5 pciclk_f (2:0) pciclk (6:0) tpci group skews at common transition edges: (un-buffered mode) group symbol conditions min typ max units 3v66 3v66 3v66 (5:0) pin to pin skew 0 500 ps pci pci pci_f (2:0) and pci (6:0) pin to pin skew 0 500 ps 3v66 to pci s 3v66-pci 3v66 (5:0) leads 33mhz pci 1.5 3.5 ns 1 guaranteed b y desi g n, not 100% tested in production. the impact of asserting the pci_stop# signal will be the following. all pci[6:0] and stoppable pci_f[2,0] clocks will latch low in their next high to low transition. pci_stop# pci_f[2:0] 33mhz pci[6:0] 33mhz assertion of pci_stop# waveforms pci_stop# - assertion (transition from logic "1" to logic "0")
15 ics932s203 0601e?12/22/04 when pd# is sampled low by two consecutive rising edges of cpu clock then all clock outputs except cpu clocks must be held low on their next high to low transition. cpu clocks must be held with the cpu clock pin driven high with a value of 2x iref, and cpuc undriven. note the example below shows cpu = 100mhz, this diagram and description is applicable for all valid cpu frequencies 66, 100, 133, 200mhz. due to the state of the internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. pd# - assertion (transition from logic "1" to logic "0") pd# functionality # p o t s _ u p ct u p cc u p c6 6 v 3t u o _ z h m 6 6 f _ k l c i c p k l c i c p k l c i c p t o d / b s u z h m 8 4 1l a m r o nl a m r o nz h m 6 6n i _ z h m 6 6n i _ z h m 6 6n i _ z h m 6 6z h m 8 4 0t l u m * f e r it a o l fw o lw o lw o lw o lw o l power down assertion of waveforms - buffered mode 0ns pd# cput 100mhz cpuc 100mhz 3v66mhz 66mhz_in 66mhz_out pci 33mhz usb 48mhz ref 14.318mhz 25ns 50ns
16 ics932s203 0601e?12/22/04 min max min max a 2.413 2.794 .095 .110 a1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c 0.127 0.254 .005 .010 d e 10.033 10.668 .395 .420 e1 7.391 7.595 .291 .299 e 0.635 basic 0.025 basic h 0.381 0.635 .015 .025 l 0.508 1.016 .020 .040 n 0 8 0 8 variations min max min max 56 18.288 18.542 .720 .730 jedec mo-118 doc# 10-0034 6/1/00 rev b n d mm. d (inch) see variations symbol see variations see variations in millimeters common dimensions in inches common dimensions see variations index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop ordering information ics932s203 y flft example: designation for tape and reel packaging lead option (optional) lf = lead free ln = lead free annealed package type f = ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device ics xxxx y f lx t
17 ics932s203 0601e?12/22/04 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (0.020 mil) min max min max a - 1.20 - .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e 0.50 basic 0.020 basic l 0.45 0.75 .018 .30 n 0 8 0 8 aaa - 0.10 - .004 variations min max min max 56 13.90 14.10 .547 .555 mo-153 jedec doc.# 10-0039 7/6/00 rev b symbol see variations see variations in millimeters common dimensions in inches common dimensions see variations 8.10 basic 0.319 n d mm. d (inch) see variations in d ex a r ea in d ex a r ea 1 2 1 2 n d e1 e s eatin g p lane s eatin g p lane a1 a a 2 a 2 e - c - - c - b c l aaa c ordering information ics932s203 y glft example: designation for tape and reel packaging lead option (optional) lf = lead free ln = lead free annealed package type g = tssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device ics xxxx y g lx t

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